Phase locked loops (PLLs) are used in data communication and telecommunication applications to lock onto the frequency of a signal. The capture range of a PLL is typically narrow. Therefore, a frequency acquisition aid is usually needed in clock and data recovery (CDR) circuits. Walker, et al. in "A 1.5 Gigabit/s link interface chipset for computer data transmission", IEEE J. Selected Areas Communication, disclosed a technique using special training data sequences. The transmit side sends special training sequences (clock-like signals) during receiver frequency/phase acquisition stage. The disadvantage is that the training sequences are not always available for all applications.
Another prior art method uses frequency detectors (FDs) that operate on the input data, and the I and Q output of the voltage-controlled oscillator (VCO). These FDs mostly can be categorized into two types: quadricorrelator and rotational frequency detector. The quadricorrelator may either be analog or digital while a rotational frequency detector is digital. An analog quadricorrelator requires many special analog components, including rectifier, differentiator, etc., as disclosed by Gardner in "Properties of Frequency Difference Detectors", IEEE Trans. Comm. It is difficult to implement and when not carefully designed, may not function properly under all conditions. The digital implementations, such as that disclosed by Pottbacker, et al. "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gigabit/s", IEEE Journal of Solid State Circuits or Messerschmitt, et al. in "Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery", IEEE Trans. Comm., have at most +/- 50% usable frequency range, but are often narrower depending on the implementation and the statistics of the input data. Due to process, temperature and VCC variations, many integrated VCOs have an upper frequency range that is more than twice, and a lower end that is less than 1/2 of their nominal frequency. Therefore these digital implementations are not adequate in this respect. Furthermore, they are also susceptible to erroneous out-of-lock indications due to jitter on the input data or isolated bit errors.
Other prior art solutions use a local reference clock. The VCO is made to frequency lock to this reference. This method is robust because it does not rely on the input data stream. Two variations are common. In the first, an externally supplied lock-to-reference control signal causes the PLL to lock to the reference clock exclusively. Having achieved frequency lock, the PLL phase locks to the data when the control is deasserted. The disadvantage is that the users must provide an extra control signal, which is not always convenient. In the second variation, a lock detector provides an automatic lock-to-reference control. The lock detector asserts this control signal when it thinks the PLL is out of lock. This lock detector operates on the input data and VCO output, similar to the frequency detector methods. This lock detector therefore has similar problems, including narrow usable frequency range, susceptibility to erroneous out-of-lock indication due to jitter on the input data or isolated bit-error events.